Design of a fault tolerant low-order interleaved memory based on the concept of bubble-stack an image storage perspective

Abstract

Memory access rates have been the shortfall of modern computing systems with increasing processor speed. High speed processors do not perform as expected due to relative low data access rates of the concerned memory. Development of a memory system with higher accessing speed is therefore the need of hour. The concept of low-order interleaved memory systems with high throughput neutralises the speed gap between processor and memory. Interleaved memory systems can also be designed in a high-order fashion to make it fault tolerant. But, a fault tolerant high-order interleaved memory lacks the speed advantage. Therefore, designing a high speed low-order interleaved memory with properties of fault tolerance remained as a challenging area of research since decades. This paper proposes a design of low-order interleaved memory system which displays a high degree of fault tolerance without compromise in speed and storage space.