FP-GNN: Adaptive FPGA accelerator for Graph Neural Networks

Abstract

Graph Neural Networks (GNNs) exhibit great success in graph data analysis and promote the evolution of artificial intelligence. The computing procedure of GNNs can be categorized into two phases: Aggregation and Combination, which have irregular and regular computing characteristics respectively. In this work, we present an adaptive FPGA accelerator, FP-GNN, to enable flexible and efficient GNN acceleration. First, this paper presents quantitative analysis of the impact on performance when changing the order of Aggregation and Combination. Then we propose an Adaptive GNN Accelerator framework (AGA) that adopts a unified processing module to support these two phases simultaneously, and an Adaptive Graph Partition strategy (AGP) to alleviate memory bottleneck and eliminate graph repartition overhead between GNN layers. In addition, we also propose multiple workflow optimizations for both Aggregation and Combination phases to achieve workload balance and feature sparsity elimination. Finally, we implement the FP-GNN on a Xilinx VCU128 FPGA, and conduct comprehensive experiments on various GNN configurations and platforms. Results show that FP-GNN achieves on average 665× speedup with 3180× energy efficiency and average 24.9× speedup with 138× energy efficiency compared to CPU and GPU, respectively, and also achieves state-of-the-art performance efficiency and energy efficiency compared to prior works.