Abstract
A novel four-quadrant /spl plusmn/1 V input, /spl plusmn/1 V output JFET analog multiplier cell is described in this work. The cell consists of one low-power operational amplifier, one commercially available dual JFET pair, three seven-resistor thin-film resistor packages, and one other trim resistor. An amplifier input offset voltage adjust and a trim resistor adjust are sufficient to yield /spl plusmn/0.5 percent of full-scale accuracy at a single temperature. The addition of a second temperature-compensated low-power amplifier results in a high input impedance multiplier with an overall accuracy of /spl plusmn/3 percent of full scale in the temperature range from 0 to 50/spl deg/C. The complete unit has a no-signal power dissipation of 0.3 mW, a full-signal power dissipation of 4 mW, and a half-power frequency response of about 10 kHz.
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