Formula omitted] double-heterostructure bipolar transistors for high-speed ICs and OEICs

Abstract

This paper describes a novel collector structure for full-potential InGaAs (FPIGA) double-heterostructure bipolar transistors (DHBTs). This new structure not only ensures high-speed operation, high breakdown and low collector turn-on voltages, but also provides pin photodiode (PD) layers suitable for high-speed and high-sensitivity operations. The FPIGA DHBT collector structure is primarily composed of relatively thick undoped, thin p +- and thin n +-InGaAs layers, and a lightly doped N-InP layer. They form a potential notch at the InGaAs InP interface at a relatively long distance from the base-collector interface, which effectively suppresses the current blocking effects arising from the conduction band discontinuity at the InGaAs InP interface. The thin p +-InGaAs layer also raises the conduction band in the collector to enhance the ballistic transport of electrons. Breakdown voltage increases because the major part of the potential change at high collector bias occurs in the N-InP layer. The layer compatibility of both the high-performance DHBTs and high-speed PDs enables us to easily manufacture optoelectronic integrated circuits (OEICs). A 1.6 × 4.6- μm 2 emitter FPIGA DHBT shows a current gain cutoff frequency, f T , of 160 GHz and a maximum oscillation frequency, f max , 162 GHz. The f T value reaches 124 GHz at low V CE of 0.65 V owing to the suppressed electron blocking effect. A small FPIGA DHBT with a 0.6 × 1.6- μm 2 emitter operates with 118 GHz f T and 148 GHz f max at an I C as low as 1 mA. The breakdown voltages of the DHBTs are high enough for any high-speed IC applications. A photoreceiver OEIC comprising a pin PD and an amplifier implemented with the FPIGA DHBTs operates error free up to 10 Gbit/s for 1.55 μm wavelength NRZ signals. For electrical inputs, the amplifier provides a transimpedance of 47.2 dBΩ with 3 dB bandwidth of 23 GHz although it has a disadvantage of parasitic capacitance of the pin PD.