Abstract
An extended formation of faceted pit-like defects on Ge(0 0 1) and Ge(1 1 1) wafers was obtained by thermal cycles to T > 750 °C. This temperature range is relevant in many surface-preparation recipes of the Ge surface. The density of the defects depends on the temperature reached, the number of annealing cycles performed and correlates to the surface-energy stability of the specific crystal orientation. We propose that the pits were formed by preferential desorption from the strained regions around dislocation pile-ups. Indeed, the morphology of the pits was the same as that observed for preferential chemical etching of dislocations while the spatial distribution of the pits was clearly non-Poissonian in line with mutual interactions between the core dislocations.
Highlights
Despite recent advances in the van der Waals epitaxy of two-dimensional semiconductors [1-7], bulk group-IV still plays a leading role in current complementary-metal-oxide-semiconductor (CMOS) technology
On the other hand, are the substrates of choice for the epitaxial growth of high-efficiency multi-junction solar cells based on III-V semiconductors [24-29] and have been shown to be suitable CMOS compatible templates for graphene overgrowth [30-32]
We found that annealing of Ge substrates above 750° may be detrimental for the quality at the mesoscale, resulting in the formation of an extended aggregation of pit-like defects at the surface
Summary
Despite recent advances in the van der Waals epitaxy of two-dimensional semiconductors [1-7], bulk group-IV still plays a leading role in current complementary-metal-oxide-semiconductor (CMOS) technology. On the other hand, are the substrates of choice for the epitaxial growth of high-efficiency multi-junction solar cells based on III-V semiconductors [24-29] and have been shown to be suitable CMOS compatible templates for graphene overgrowth [30-32] All these applications require a highlydemanding surface quality of the epi-ready Ge substrates. While COPs are voids produced by the aggregation of vacancies, it is generally assumed that the formation of L-pits is related to dislocation loops either intrinsically formed during the wafer manufacturing [34, 35] or by misfit strain in the case of SiGe heteroepitaxy [36]. L pits at the substrate are too large to be buried within an epilayer film which will be damaged by their presence These imperfections are detrimental for the final performance and the production yield of any device monolithically grown on Ge substrates. The pits demonstrate wall patterns typical of dislocation-pinning on swirl defects
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