Abstract

Cryptographic circuits are essential in systems where security is the main criteria. Therefore, it is crucial to ensure the correctness of not only the cryptographic algorithms, but also their hardware implementations. Formal methods, unlike the other validation techniques, guarantee the absence of errors.The problem is that designers still use conventional Hardware Description Languages (HDLs), which are poorly suited for formal verification. This paper presents a verificationmethodology for the pipelined cryptographic circuits using for-mal methods in an automatic manner. It consists on using the functional HDL Lava to describe and verify the equivalence between the behavioral specification and structural implementation of a circuit. To the best of our knowledge, we are the first to use this functional HDL for that computpurpose. To show the features of the proposed approach, it was applied to verify the pipelined implemen-tation of the cryptographic circuit AES (Advanced Encryption Standard).

Highlights

  • Cryptography plays a major role in modern applications, as the present networks are trusted with highly sensitive information; cryptographic circuits have become indispensable in these systems

  • We demonstrate how we applied our approach for verifying the pipelined cryptographic circuit Advanced Encryption Standard (AES)

  • The proposed approach consists of a formal design and verification methodology for the pipelined cryptographic circuits using a functional Hardware Description Languages (HDLs)

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Summary

Introduction

Cryptography plays a major role in modern applications, as the present networks are trusted with highly sensitive information; cryptographic circuits have become indispensable in these systems. To ensure the security of information, the cryptographic algorithms have to be verified and their hardware implementations. The first step of the design process consists in the conversion of the informal description of the design to a formal Behavioural (or Algorithmic) specification. From this latter, a Structural (or Micro-architectural) implementation is derived through refinement, followed by a sequence of design steps that reduce the abstraction levels until a realizable description is obtained. We demonstrate how we applied our approach for verifying the pipelined cryptographic circuit Advanced Encryption Standard (AES).

Related works
Contribution of this work
The proposed approach
Application and results
Behavioural specification of the AES circuit
AES sequential architecture
AES pipelined architecture
Formal verification of the AES circuit
Conclusion
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