Abstract
Latency-insensitive design (LID) theory was invented to deal with SoC timing closure issues, by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with using a resynchronization protocol that performs dynamic scheduling of data transportation. Functional behavior is preserved. This dynamic scheduling is implemented using specific synchronous hardware elements: relay-stations (RS) and shell-wrappers (SW). Our first goal is to provide a formal modeling of RS and SW, that can be then formally verified. As turns out, resulting behavior is k-periodic, thus amenable to static scheduling. Our second goal is to provide formal hardware modeling here also. It initially performs throughput equalization, adding integer latencies wherever possible; residual cases require introduction of fractional registers (FRs) at specific locations. Benchmark results are presented, run on our KPASSA tool implementation.
Highlights
Long wire interconnect latencies induce time-closure difficulties in modern SoC designs, with propagation of signals across the die in a single clock cycle being problematic
The issue arises in our running example only at the topmost computation node. We indicate it by prefixing some of the inactive steps (0) in its schedule by symbols: lack of input from the right input link (’), or from the left one (‘)
The purpose of shell-wrappers is to trigger the local computation node exactly when tokens are available from each input link, and there is storage available for result in output links
Summary
Long wire interconnect latencies induce time-closure difficulties in modern SoC designs, with propagation of signals across the die in a single clock cycle being problematic. Computation blocks may be temporarily paused at times, either because of input signal unavailability, or because of the inability of the rest of the networks to store their outputs if they were produced This latter issue stems from the limitation of fixed-size buffering capacity of the interconnects (relaystation lines). We provide some definitional and notational background on various models of computations involved in our modeling framework, together with an explicit representation of periodic schedules and firing instants; with this we can state historical results on k-periodic scheduling of WMGs. In Section 3, we provide the synchronous reactive representation of relay-stations and shell-wrappers, show their use in dynamic scheduling of latency-insensitive design, and describe several formal local correctness properties that help with the global correctness property of the full network.
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