FM Receiver Design Using Programmable PLL

Abstract

The research article presents the design of different components of FM receiver. The design approach is based on digital components rather than analog components such as phase detector, loop filter and voltage controlled oscillator. The signal is presented using digital words instead of analog voltages. In digital FM receiver, PLL is the main part to capture and lock the signals at different frequency and phase. The main purpose of PLL is to maintain the coherence between the modulated signal frequency (fi) and the respective frequency (fo), with the concept of phase comparison. PLL permits to track the frequency changes of applied input signals, as it is locked once. There is a use of 8 bit analog to digital conversion circuit, which is accepting frequency modulated signal as a series of digital numerical values. The same signals are demodulated by the receiver on every clock cycle. The paper proposed the design and FPGA implementation of digital PLL and programmable all FM receiver. The design is developed in Xilinx 14.2 ISE software and simulated in Modelsim 10.1b software with the help of VHDL programming language and the targeted onVirtex-5 FPGA.