Flowpaths: Compiling stack-based IR to hardware

Abstract

The performance of software executed on a microprocessor is adversely affected by the basic fetch–execute cycle. A further performance penalty results from the load–execute–store paradigm associated with the use of local variables in most high-level languages. Implementing the software algorithm directly in hardware such as on an FPGA can alleviate these performance penalties. Such implementations are normally developed in a hardware description language such as VHDL or Verilog. More recently, several methods for using C as a hardware description language and for compiling C programs to hardware have been researched. Several software-programming languages compile to an intermediate representation (IR) that is stack based such as Java to Java bytecodes. Forth is a programming language that minimizes the use of local variables by exchanging the load–execute–store paradigm for stack manipulation instructions. This paper introduces a new systems architecture for FPGAs, called flowpaths, which can implement Java bytecodes or software programs written in Forth directly in an FPGA without the need for a microprocessor core. In the flowpath implementation of Forth programs all stack manipulation instructions are represented as simple wire connections that take zero time to execute. In the flowpath implementation of Java bytecodes the normal load–execute–store paradigm is represented as a single sequential operation and stack-manipulation operations become combinational thus executing faster. This paper compares the use of flowpaths in an FPGA generated from Java bytecodes and a high-level Forth program for the Sieve of Eratosthenes with C, Java, and Forth executed on microprocessors and microprocessor cores on FPGAs. The results show that flowpaths perform within a factor of two of a minimal hand-crafted direct hardware implementation of the Sieve and orders of magnitude better than compiling the program to a microprocessor.