Abstract
It is practical and crucial that a designer will want to control the positions of some modules along the chip boundary in the final packing for I/O connection. To solve the problem we propose an algorithm named Area Estimate Transitive Closure Graphs (AE-TCG). By analyzing the feasible condition of boundary constraints, AE-TCG guarantees that the result of each perturbation is a feasible placement with boundary constraints, and doesn’t need to transform the infeasible solution to feasible one. Unlike most of the previous algorithms getting the target area after packing, AE-TCG can satisfy the boundary constraints and estimate the area of feasible placement without packing after random perturbation, then accept the beneficial perturbation. For the property of concentrate itself, AE-TCG is running without Simulated Annealing (SA) process. The experimental results show that AE-TCG is effective and efficient than other algorithms with boundary constraints in commonly used MCNC benchmark circuits.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call