Flip chip packaging

Abstract

Some of the needs for improved performance can be met with versions of the packaging solutions that have been developed over the last 5-10 years. These solutions have typically focused on peripheral packages with wire bond chip-to-package interconnects. As the number of leads increases, this type of package becomes problematical. An alternative to peripheral interconnect packaging is to access the unused area under the chip and package for interconnects in an area array. In area array packaging, the surface of the chip has an array of solder interconnects (solder bumps) that are joined to a substrate when the chip is flipped over (flip chip packaging). The interconnects are then redistributed through the BGA substrate. Even with the advantages created by area array packaging, processing, performance, reliability, and cost requirements are challenging currently available area array electronic package design. This paper addresses some of the critical challenges facing flip chip electronic packaging.