Issues in fatigue life prediction model for underfilled flip chip bump

Abstract

Flip Chip (FC) technology has now become mainstream solution for high-performance packages. From commercial gaming machines to high-reliability servers, FC package is gaining more market share over traditional packaging technologies, such as wire bond. Extensive research has been carried out in FC technologies to improve reliability with increasing IO density. In a flip chip package, thermal mismatch between the silicon die, and the substrate causes solder bump failure due to thermal cycling. Typical failures like bump fatigue, package warpage, die low-k or ELK delamination, die backside crack, BGA joint fatigue are still the major challenges in flip chip packages. Appropriate underfill can significantly reduce the risk of bump cracking by reducing stresses on solder bumps. Due to the complex nature of underfilled flip chip package, accurate failure prediction in accelerated or field life condition is very problematic. There are some good predictive models for package warpage, die low K delamination, and BGA fatigue life that have been published in the literature with varying level of accuracy, however, there is no strong predictive model for flip chip bump life prediction with underfill. Very often researchers use BGA fatigue model for flip chip bump life prediction that end up with huge discrepancy with the actual data. Specifically, the interaction between the underfill material and solder bumps is still unknown. Moreover, there is no good modeling methodology for flip chip bump life prediction. Unlike board level reliability testing, most of the package level testing done for flip chip reliability use qualification testing approaches where the test is suspended after a set number of cycles and pass/fail criteria is based on open/short testing after the conclusion of test. This creates difficulty in correlating simulation results with actual life. In this effort, a large die Pb free flip chip test vehicle has been designed to monitor in-situ bumps and BGA joints crack during temperature cycle. Wide range of material variables such as substrate core type, underfill type, package type, and test conditions have been considered in this study. Through this comprehensive package evaluation and simulation studies, both bump and BGA in-situ data for underfilled packages will be collected and to help develop accurate Pb free bump fatigue model for flip chip bumps.