Flip Chip Assembly on Coreless Substrate Challenge with Die Bond Solution

Abstract

Flip Chip Packages are the popular packages in many different applications. Flip Chip can provide the ideal solution for low I/O to high I/O, high electrical performance demand in where high frequency, high speed are required. By using coreless substrate with embedded fine-trace substrate (ETS) technologies to achieve package miniaturization requirement.Comparing with conventional substrate, coreless substrate technologies eliminate the substrate core, and utilize substrate layers to interconnect the chip and the PCB board. It brings benefits not only with low Z-height, lightweight, but also offers short interconnection distance and good signal integrity. The ETS coreless technology is a promising solution for the next generation substrate. To approach these requirements, we would like to discuss the suitable process for laser assisted bonding (LAB), thermal compression bonding (TCB) combining with molding underfill (MUF) technology and comparing with traditional mass reflow (MR). A Flip Chip Package and ETS coreless substrate combination are used for this paper experiment. The major challenge is thinner ETS coreless substrate will induce more warpage concern because of no rigid core material as supporting structure, thus ETS coreless substrate with less stiffness, is easier to bring handling issue during assembly manufacturing process. Thermal compression bonding could offer less stress to reduce CTE mismatch between silicon chip and coreless substrate. The study result of warpage comparison among TCB, LAB and mass reflow process, shows that the TCB could provide less warpage. Furthermore, TCB technology is popular used for thin core, coreless and advance silicon node product field. For LAB, it can provide the better throughput than TCB, and also provide more accuracy fine pitch bonding than MR.