Flicker-Noise Impact on Scaling of Mixed-Signal CMOS With HfSiON

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The flicker noise in MOSFETs with short gate lengths <formula formulatype="inline"><tex>$(L ≪ \hbox{1}\ \mu \hbox{m})$</tex></formula> is severely degraded by the presence of a thick high-<formula formulatype="inline"><tex> $k$</tex></formula> gate dielectric layer. The gate length dependence of flicker noise becomes stronger with increasing high-<formula formulatype="inline"><tex>$k$</tex></formula> dielectric thickness—but only for n-FET. To explain these phenomena, a model based on excess traps at the gate edges has been developed. This model explains the flicker-noise dependence on high-<formula formulatype="inline"><tex>$k$</tex></formula> dielectric thickness and gate length and has successfully reproduced the experimental data. Based on the model, the impact of gate-length scaling is evaluated for future mixed-signal ICs using high-<formula formulatype="inline"><tex>$k$</tex> </formula> gate-dielectric technology. The deployment of high-<formula formulatype="inline"><tex>$k$</tex></formula> gate dielectric adds another gate-length-scaling limit for analog devices due to the noise consideration. </para>