Flexible Multicore System Based on Globally Asynchronous Locally Synchronous Core

Abstract

This Synchronous (clocked) design is still by far the most accepted digital system design methodology, well implicit and supported by the established CAD tools. Multi-core processors system should be flexible enough to provide high throughput for standardized parallel applications as well as high performance for more precise work. To reduce the memory wall for applications with high memory-level parallelism. The micro architecture contains a set of small and fast cache Processors(CP) that execute high locality code and a network of Small in-order memory engines that together use low locality code. To improve performance through uses instruction level parallelism, thread-level parallelism. We proposes the Flexible Heterogeneous Multi Core system (FMC), according to study of different flexible/scalable architecture of heterogeneous multi-core system the first dynamic heterogeneous multi-core architecture capable of reconfiguring itself to fit application requirements. The basic of this micro architecture is a scalable and flexible. Globally Asynchronous Locally Synchronous (GALS) processor outperformed the synchronous processor in terms of operating frequency which is approximately double the frequency of its synchronous version. GALS is a relatively new VLSI system design methodology that promises to combine the advantages of both synchronous and asynchronous designs. Through the proposed design, our aim is to bring forward the advantages of asynchronous design as much as possible. The synthesis results show that under the same power consumption and a small area overhead, Here different functional blocks have different clock. And it is necessary according to their requirements and operating frequencies. To the complete and whole system distributing a high frequency global clock with low skew is a difficult task demanding a lot of design effort, die area and power.