Flexible Matrix of Controllers for Real Time Parallel Control

Patryk Chaber,Andrzej Wojtulewicz

doi:10.3390/en15051833

Abstract

This work aims to develop a novel system, including software and hardware, to perform independent control tasks in a genuine parallel manner. Currently, to control processes with various sampling periods, distributed control systems are most commonly utilized. The main goal of this system is to propose an alternative solution, which allows simultaneous control of both fast and slow processes. The presented approach utilizes FPGA (Field Programmable Gate Array) with Nios II processor (Intel Soft Processor Series) to implement and maintain instances of independent controllers. Instances can implement FDMC (Fast Dynamic Matrix Control) and PID (Proportional-Integral-Derivative) control algorithms with various sampling times. The FPGA-based design allows for true independence of controllers’ execution both from one another and the managing processor. Also, pure parallel execution allows for implementing slow and fast controllers in the same device. The complete flexible system with a matrix of controllers working in parallel in real-time was tested with both simulated and actual control processes (servomotor), yielding the same results as fully simulated experiments.

Highlights

As the Model Predictive Control (MPC) [1,2] approach is expanding from industrial processes with long sampling periods to processes with sampling periods of single milliseconds [3–5] or even microseconds [6,7], there is a demand for controllers executing and calculating new control signals on time
The analogous experiment was performed with the testing environment, and with a real-life servomotor connected via ADC and PWM, and two internally implemented in the FPGA simulated processes
The authors presented the novel design of the control system based on the FPGA unit, which allows running independent controllers with various intervention times in an organized manner

Summary

Introduction

Some papers aim for the robustness of the control algorithms despite uncertainties [12,13], unknown disturbances [14] or unknown model of the controlled process [15]. This phenomenon is coupled with a still-growing interest in MPC in embedded systems, including microcontrollers [6,16] and Field Programmable Gate Arrays [17–19], which, despite having much more limited resources, can be utilized for controlling complex, nonlinear processes [20,21]. It is possible to achieve more than 100 times algorithm speedup by using process decomposition and computation parallelization [24,25]. The use of FPGAs in the multiplication of integer with notation matrices was presented in the work of [26], where the optimal use of multiplication circuits reduced the use of logic resources and increased the speed of computation

Objectives

Results

Conclusion