Abstract
Hardware implementation aspects of highly flexible low-density parity-check (LDPC) encoder and decoder are presented. The paper covers algorithmic and architectural approaches in achieving flexible and yet very efficient LDPC codec solutions in terms of hardware usage efficiency (HUE). LDPC encoder is implemented to support all possible codes from the 5G New Radio (NR) communication standard, whereas LDPC decoder supports any quasi-cyclic (QC) LDPC or QC-LDPC like code family. Both architectures were optimized using genetic algorithm (GA) for higher throughput or better error correcting (EC) performance results.
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