Abstract
To reduce the gap between the VLSI technology capability and the designer productivity, design reuse based on IP (intellectual properties) is commonly used. In terms of arithmetic accuracy, the generated architecture can generally only be configured through the input and output word lengths. In this paper, a new kind of method to optimize fixed-point arithmetic IP has been proposed. The architecture cost is minimized under accuracy constraints defined by the user. Our approach allows exploring the fixed-point search space and the algorithm-level search space to select the optimized structure and fixed-point specification. To significantly reduce the optimization and design times, analytical models are used for the fixed-point optimization process.
Highlights
Advances in VLSI technology offer the opportunity to integrate hardware accelerators and heterogenous processors in a single chip or to obtain FPGAs with several millions of gate equivalent
The third generation of mobile communication system requires implementing in a digital platform the wide band code division multiple access (WCDMA) transmitter/receiver, a turbo-decoder, and different codecs for voice (AMR), image (JPEG), and video (MPEG4)
An infinite impulse response filter (IIR) intellectual properties (IP) is under consideration
Summary
Advances in VLSI technology offer the opportunity to integrate hardware accelerators and heterogenous processors in a single chip (system-on-chip) or to obtain FPGAs with several millions of gate equivalent. As shown in the experiment presented, for a same architecture the signalto-quantization-noise ratio (SQNR) can vary from 30 dB to 62 dB for different structures This search space must be explored and the adequate structure must be chosen to reduce the chip size and the power consumption. This algorithm level search space cannot be explored with available IPs without a huge exploration time. The fixed-point conversion is automatically achieved through the determination of the integer and fractional part word lengths. These IPs are configurable according to accuracy constraints influencing. The optimal operator word lengths which minimize the architecture cost and respect the accuracy constraint are searched. The LMS/DLMS application case is developed and the experiments are detailed with IIR applications
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