First-Order Recursive CIC Filters in Time-Interleaved VCO-Based ADCs for Direct-RF Sampling Receivers

Abstract

Digital building blocks operating at gigasamples per second (GS/s) rates in direct radio frequency (RF) sampling receivers consume a large amount of the total power of the receivers. The previously reported techniques have not considered the digital blocks in analog-to-digital converters (ADCs) and not decreased the power consumption. We first place first-order recursive cascaded integrator-comb (CIC) filters with decimation factors of two after time-interleaved ADCs (TI-ADCs), consisting of voltage-controlled oscillators (VCOs), samplers, phase detectors, and differentiators. This CIC filter cancels out the differentiators with its integrators and halves the clock frequencies of the samplers to reduce the power consumption of the receiver. We design the digital blocks of a direct-RF sampling receiver with a 3.6-GS/s 4-channel TI VCO-based ADC for Sub-GHz applications (phase detectors, mixers, and CIC filters) by using a 65-nm CMOS process. Simulations show that the place-and-routed circuit operates at a 450-MS/s rate with 3.6 mW, which is half of the power consumption of a digital circuit without the proposed method.