Abstract
This work describes a methodology to extract parasitic capacitances and evaluate losses in multifinger thermally shunted heterojunction bipolar transistors (HBTs) using three dimensional (3-D) electromagnetic modeling. This method is based on the partitioning of the structure into zones of propagation, which simplifies the analysis of the computed scattering matrices. The approach is validated using on-wafer measurements of open-circuit test structures. This work also addresses the impact of changes in device topology on parasitic coupling capacitance and association efficiency.
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