Abstract

Stacked chip scale packaging (SCSP) has been an increasingly important approach for realizing high density 3D packaging. During SCSP process, package will endure several thermal loadings, such as die attach (DA) cure, post-molding cure and reflow. Thermal stress may result in die crack or delamination before package is finished if thermal mismatch between internal packaging materials is too much. In this study, packaging process for a typical four-chip SCSP product, FTA073, is studied in detail. Finite element analysis (FEA) has been applied in three major process steps which experience temperature change for package failures in die crack or delamination, including the 1st DA cure (cure I), the 2nd/3rd/4th DA cure (cure II) and post-molding cure (cure III). Our process simulation demonstrates that cure II would be the most destructive by comparing the influence of these three curing processes on SCSP reliability. It is also found that, in cure I and cure II a certain distribution stress with typical characteristics is formed on package block which consists of 15 unit packages, however, no such characteristics was formed in step cure III. Our investigation would be beneficial to reducing package failures and increasing yields during packaging process

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