Challenges in Stacked CSP Packaging Technology

Abstract

The electronics industry trend is to offer products that are smaller, with more functionality, better performance and lower cost. Stacked chip scale packaging (CSP) is an innovative packaging technique that involves thinning silicon to enable multiple chips to be stacked in a package for integrated solution. Stacking memory chips and stacking memory and logic chips together are two typical approaches in stacked CSP technology. Combining chips of different sizes is more difficult than adding similar-size chips to a package. Approach in stacked CSP of different die sizes and package configuration will be discussed in this paper.