Finite Element Analysis and Measurement of Low-Profile BVATMPackage On Package (PoP) Warpage Characteristics

Abstract

Mobile electronics developers continue to demand lower-profile components in order to achieve thinner, higher-performing handheld products. This requirement extends to the commonly used Package-on-Package (PoP) configuration where recent trends are demanding 1.0mm or less total height for the stacked processor and memory components. Bond-Via-Array (BVTM technology facilitates next-generation Package-on-Package (PoP) by utilizing wirebond technology to achieve fine-pitch interconnects at controlled height. As with conventional PoP, thinner components present challenges to controlling the resulting package warpage. It is important to understand the warpage behavior of both the base Logic and topside memory packages in order to ensure a high-yielding stacking process. Limiting warpage to below 100um is critical for manufacturing as well as meeting thermo-mechanical reliability standards. Design and material selection for both components influence the warpage profiles. Utilizing Finite Element Analysis (FEA) we examine the influence of the overall structure and key material selection on package warpage in order to determine configurations for further reducing BVA PoP stack height. Analysis is based on a 1020 IO 14mm×14mm outline package test vehicle. A detailed analysis of results includes comparison of simulation data with measurements of actual samples with various materials and thicknesses. The FEA model is validated with prototype packages by measuring actual warpage as a function of temperature. Experimental data for exposed die and over-molded die samples are included in the completed results and analysis.