Finite Arithmetic Considerations for the FFT Implemented in FPGA-Based Embedded Processors in Synthetic Instruments

Abstract

An important trend in the synthetic instrument community is the development of products around the capabilities of field programmable gate array (FPGA) based embedded processors. It is assumed here that signals arrive at the FPGA input at high data rates, low to medium data bit width, and low to medium signal-to-noise ratio. As a consequence of the processing that reduces signal bandwidth, the data bit width is increased in concert with the increased signal-to-noise ratio resulting from the reduced bandwidth. The FPGA has the unique capability to allocate its internal resources in an optimal way to best match the dynamic range of the sampled data signal at various points in the signal flow path. Since the fast Fourier transform (FFT) is primarily a tool in the synthetic instrument, the effect of fixed point arithmetic on its performance is reviewed, and suggested bit width assignments for FFT algorithms are presented. Computational noise in the FFT is due to finite bit width input data, finite bit width sine-cosine tables, finite bit width multipliers and accumulators, and distributed scaling between data passes. The noise generated by these contributors is not uniform over the frequency band and a number of mechanisms to minimize the noise contribution to the measurement process performed by the synthetic instrument are presented.