FinFET-Premised 1-Bit Comparator Design Using CPTL and DCVSPG Techniques

Abstract

For the efficient design of digital circuits many digital designing techniques have been characterized by Pass Transistor Logic family. Pass transistor-based techniques prefer N-channel devices for the logic implementation as compared to static CMOS which helps in achieving better performance at ultra-scaled technology nodes. We in this work have designed 1-bit comparator circuits by deploying Complementary Pass Transistor Logics (CPTL) and Differential Cascode Voltage Switch with Pass Gate (DCVSPG) techniques. The comparative analysis of these two techniques based 1-bit comparator circuits has been presented in FinFET 18 nm technology. The results show that CPTL premised 1-bit comparator emulates power dissipation of 58720 nW, propagation delay of 750. S5 ns, power delay product (PDP) of44.08 pJ and energy delay product (EDP) of33.09 aJs. In contrast to CPTL premised 1-bit comparator, the DCVPSG premised 1-bit comparator emulates power dissipation of 59870 nW, propagation delay of 500.64 ns, power delay product (PDP) of 29.97 pJ and energy delay product (EDP) 15 aJs. Although, the power dissipated by DCVSPG based 1-bit comparator is more as compare to CPTL based design but it is showing its efficiency in terms of all other considered factors for comparative analysis.