Design and Analysis of Power Efficient 1-bit Adder circuits in 18 nm FinFET Technology

Abstract

Implantable electronics demand for ultra-low power techniques at nanometer regime. Due to limitations of CMOS technology new logic circuit using next generation devices are required to be developed. In this work, FinFET based one-bit adder circuits are designed using Complementary FinFET Technique (CFT) and Complementary Pass Transistor Logic (CPTL) in 18 nm FinFET technology. The results show values of Power Delay Product (PDP) and Energy Delay Product (EDP) for CFT based one-bit adder circuit are 6905. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$130 \mathrm{x}10^{-15}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6981.565 \mathrm{x} 10^{-22}$</tex> respectively. Whereas, values of PDP and EDP for CPTL based one-bit adder circuit are <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6460 \mathrm{x}10^{-15}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6137 \mathrm{x}10^{-22}$</tex> . CPTL based design is showing better efficiency in terms of power and energy delay product. The FinFET based CPTL adder circuit outlined in this work are expected be used in low-power portable and implantable biomedical systems.