Design of a low power, high speed and energy efficient 3 transistor XOR gate in 45nm technology using the conception of MVT methodology

Abstract

This paper puts forward the design of a low power, high speed and energy efficient XOR gate comprising only 3 transistors in 45nm technology using the conception of Mixed Threshold Voltage (MVT) methodology. On comparison with the conventional CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL), the proposed design showed a substantial amount of depreciation in Average Power consumption (P avg ), Peak Power consumption (P peak ), delay time, Power Delay Product (PDP) and Energy Delay Product (EDP), respectively. It has been found that Pavg is as small as 6.72×10 -11 W while P peak is as small as 1.11×10 -6 W. On further computation, it has been found that delay time is as low as 1.05pico second and hence PDP is as small as 7.07×10 -23 Joule whereas EDP is as less as 7.45×10 -35 Js for 0.9 volt power supply. In addition to this, due to reduced transistor count, surface area is also remarkably reduced. The simulation for the proposed design has been carried out in Tanner S PICE and the layout has been concocted in Microwind.