FinFET—Based Low Swing Rotary Traveling Wave Oscillators

Abstract

FinFET based, low swing clocking with rotary traveling wave oscillators (RTWO) is presented in this paper. It is shown that the low-swing clock signal generation by RTWOs is very effective, thanks to FinFETs accommodating high frequency operation and voltage scaling better than planar CMOS transistors. Low swing clocks are aimed at lowering the power dissipation of the clock networks, while maintaining the full voltage operation of non-clock components (such as logic and memory). In this work shows that robust low swing (LS) RTWOs are designed with FinFET based technologies. To this end, SPICE simulations are performed on the ISPD'10 clock benchmark circuits operating at 2.25 GHz and 3 GHz in the 16 nm FinFET technology node. LS-RTWO based designs are compared to an all digital phase locked loop (ADPLL) based designs operating at the same target frequency. At 3 GHz, the LS-RTWO consumes 36% lower power with 42.7dB better phase noise @10 MHz on comparison to corresponding ADPLL based designs.