Finfet based Frequency Divider Design Using True Single Phase Clock Technique

Abstract

FinFETs are superior than CMOS in terms of area, power and voltage. The short channel effects are greatly reduced in FINFETs compared to planar technology. True Single Phase clock is a dynamic circuit architecture to use only a single clock signal without inverting. Since the inverted clock signal is used in the design, clock skew problems does not exist. The technique also reduces the silicon area required for clock lines. This helps the designer to achieve higher clock frequencies for dynamic pipelined operations. In high performance based designs, TSPC based circuits are preferred alternative to conventional circuits. The paper explains the implementation of frequency divider circuit using FinFET based T flip flops built using TSPC technique. The design and simulation is carried out using cadence EDA and virtuoso tool in 18nm technology.