Fine pitch copper PoP for mobile applications

Abstract

Today, memory plus logic stacking is being provided to smartphones and tablet computers by means of Package-on-Package (PoP). However, current PoP top-to-bottom interconnect technologies do not efficiently scale to provide the memory bandwidth required for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap or using PCB interposers are not cost effectively achieving required aspect ratios for fine pitch while overcoming package warp during soldering. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology is studied that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. It is shown that the there are multiple methods for forming the wire-bonds, exposing the wires above the molded package body and connecting the top package to these wires. These results show that wire-bond interconnect technology is promising for the very high density and fine pitch required for wide IO implementations.