Finding the Best Compromise in Compiling Compound Loops to Verilog

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We consider a special optimization problem involved with compiling compound loops (combining nested and consecutive sub-loops) with array references to Verilog. Each sub-loop of the compound loop may require a different optimized hardware configuration (OHC) for optimized execution times. For example, one loop requires at least two memory ports and one multiplier for an optimized execution time while another loop may require only one memory port but two multipliers. The goal is to compute a minimal OHC which, based on the different execution frequencies of the sub-loops, is a good compromise between all the conflicting requirements of each sub-loop. Though synthesis of nested loop has been implemented in quite a few systems this aspect has not been considered so far. The proposed solution is based on a novel search procedure that efficiently explores the exponential combinations space of possible OHCs. We avoid the use of Integer Linear Programming (ILP) techniques and use instead a fast space exploration technique that is combined with an efficient variant of List scheduling. Another novel aspect of the proposed system is the observation that the delays/latencies of the hardware units should be considered as variables of the OHC rather than fixed real values as is usually done in high level synthesis systems. Experimental results shows a significant improvement of the OHC and power consumption without a significant increase in the execution time due to use of this search procedure.