Fin core dimensionality and corner effect in dual core gate-all-around FinFET

Abstract

This article proposes investigation of low power performance of a fin field-effect transistor (FinFET) with surrounding gates through a calibrated technology computer-aided design (TCAD) framework. The proposed silicon body FinFET has a dual core structure in its source and drain regions, which offers opportunities for tuning its performance in terms on current, off current, threshold voltage and sub-threshold swing. Through variation of height and width of inner and outer cores, different electrical parameters are reported. To assess the impact of corner effect on device performance, gate edge suppression is introduced from all four sides, and their effects are reported for two cases: one, with equal suppressions, and the other, with suppressions in a 2:1 ratio. The percentage of occupancy of the inner core with respect to the overall volume of the source/drain decides the electrical parameters for different cases of core dimensions. For a 35 % reduction in the channel length, the overall low power performance of the device improves.