Field Programmable Gate Arrays

Abstract

The traditional field programmable gate array (FPGA) design flow creates a register transfer level abstraction using a hardware description language. This chapter briefly introduces some of the terms and definitions related to FPGA architecture and design flow for hardware‐in‐the‐loop emulation. The logic resources of multi‐processing system‐on‐chip are typically lower than the FPGA device with the same manufacturing technology. Due to the complex routing and additional combinational and sequential logics inferred for reconfiguration on FPGA, the clock frequency of such a device is lower than that of the processing system. Both Xilinx VCU118 and ZCU102 boards have plenty of components and communication interfaces, such as double data rate fourth‐generation memory, quad serial peripheral interface flash, general purpose IO, FPGA mezzanine interface, and small form‐factor pluggable interface. Parallel and pipeline paradigms are two interesting features for FPGA programming to improve computational speed and throughput.