Field effect transistor test structures for p-stop strip isolation studies

Abstract

The strip isolation of AC-coupled n-on-p silicon strip sensors is compromised by positive charges located in the oxide above the silicon bulk. These positive oxide charges form an inversion layer electrically interconnecting the n+-implanted strips. To achieve a proper strip isolation though, a p+-implantation, the p-stop, is usually inserted in between the strips. The properties of this implantation like the concentration or implantation depth influence the final strip isolation. To investigate the isolation capability of the p-stop, field effect transistor (FET) test structures have been designed, measured and simulated using Synopsys TCAD. The main goal of these studies is to relate the threshold voltage of such transistors to the inter-strip resistance of actual sensors. Therewith, extensive measurements of usually large resistances could be transferred to comparable simple ones.