Abstract
The Front-End Link eXchange (FELIX) system is an interface between the trigger and detector electronics and commodity switched networks for the ATLAS experiment at CERN. In preparation for the LHC Run 3, to start in 2022, the system is being installed to read out the new electromagnetic calorimeter, calorimeter trigger, and muon components being installed as part of the ongoing ATLAS upgrade programme. The detector and trigger electronic systems are largely custom and fully synchronous with respect to the 40.08 MHz clock of the Large Hadron Collider (LHC). The FELIX system uses FPGAs on server-hosted PCIe boards to pass data between custom data links connected to the detector and trigger electronics and host system memory over a PCIe interface then route data to network clients, such as the Software Readout Drivers (SW ROD), via a dedicated software platform running on these machines. The SW RODs build event fragments, buffer data, perform detector-specific processing and provide data for the ATLAS High Level Trigger. The FELIX approach takes advantage of modern FPGAs and commodity computing to reduce the system complexity and effort needed to support data acquisition systems in comparison to previous designs. Future upgrades of the experiment will introduce FELIX to read out all other detector components.
Highlights
The ATLAS experiment at CERN [1] explores collisions of protons and heavy ions from the Large Hadron Collider (LHC) to study physics at the energy frontier
The Front-End Link eXchange (FELIX) system serves as an interface between these links and commodity switched networks
By Run 4, the FELIX system will be installed to read out all detector components
Summary
The ATLAS experiment at CERN [1] explores collisions of protons and heavy ions from the Large Hadron Collider (LHC) to study physics at the energy frontier. The LHC accelerates bunches of particles to up to 6.5 TeV and collides them every 25 ns at a combined energy up to 13 TeV It is imperative for the on-detector electronics systems to run synchronously with the LHC clock to digitize the detector signals. The FPGA allows us to handle data transmissions and to route data between the detector links and the PCIe interface. The FELIX approach was facilitated by the rapid development of commodity switched networks, server CPUs and FPGAs. FELIX reduced the need to develop custom electronics and firmware in comparison to the previous data acquisition architecture. A prototype FELIX board for the Run 4 upgrade has been designed It features a Xilinx Versal Prime FPGA and 24 optical data links. A final decision on the hardware platform won’t be made for some time, but ongoing studies with this prototype and its successors will make it possible to closely track technological evolution
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