FDTD analysis of CMOS microstrip structures

Abstract

The FDTD method is used to model microstrip structures fabricated using a 0.35 /spl mu/m CMOS process. Modeling thin metal and oxide layers of 1 /spl mu/m thickness results a very small vertical cell size. As a consequence, a very short time step is required to ensure stability. This turn results difficulties obtaining simulation data below 20 GHz without resorting to all excessive number of time steps. In this paper, we investigate microstrip structures fabricated on a thin oxide layer from the computational point of view. The problem is to obtain accurate low-frequency data while (i) using a small cell size to accurately model the layer structure resulting a short time step, and (ii) using a limited number of time steps to reduce the simulation time. To accomplish this, the simulation is excited using a resistive source resulting fast decay of the incident field. To excite TEM mode the microstrip, a model to connect the source across multiple cells in parallel is presented. Finally, the frequency resolution is improved by using the frequency-shifting technique. The results are validated by comparison to experimental data at 0.5-20 GHz measured using an on-wafer probe station.