Fault Tolerant Modified Asymmetric MLI Topologies with Reduced Switch Count

Abstract

The goal of this research work, is to enable fault tolerance in Multilevel Inverter (MLI) technique utilizing Asymmetric Reduced Switch Count (ARSC). In Symmetric Reduced Switch Count (SRSC) inverters possible switching sequence is less for a specific output voltage level. Due to the reduced device count, the lack of redundant states impacts the capability of fault tolerant operation and severely compromises the inverter’s reliability, which resulting in the system’s complete shutdown. Whereas in ARSC inverters redundant states are almost naught for various inverter output voltage levels. Therefore, in this proposed paper the operation of a seven-level asymmetric inverter is analyzed in the event of single and double open switch failures. The general structure of an asymmetric seven-level inverter is modified by inclusion of bidirectional switches and two new asymmetric inverters topologies have been proposed with fault tolerant operational facility. The proposed topologies sustain output voltage either at five level or three level for an open switch fault in one or two switches. Circuits were simulated in the simulation of MATLAB environment and outcomes were checked in order to validate the efficacy of suggested topologies.