Abstract
This paper deals with the modeling of fault for analog circuits. A two-dimensional (2D) fault model is first proposed based on collaborative analysis of supply current and output voltage. This model is a family of circle loci on the complex plane, and it simplifies greatly the algorithms for test point selection and potential fault simulations, which are primary difficulties in fault diagnosis of analog circuits. Furthermore, in order to reduce the difficulty of fault location, an improved fault model in three-dimensional (3D) complex space is proposed, which achieves a far better fault detection ratio (FDR) against measurement error and parametric tolerance. To address the problem of fault masking in both 2D and 3D fault models, this paper proposes an effective design for testability (DFT) method. By adding redundant bypassing-components in the circuit under test (CUT), this method achieves excellent fault isolation ratio (FIR) in ambiguity group isolation. The efficacy of the proposed model and testing method is validated through experimental results provided in this paper.
Highlights
Over the past two decades, fault detection and diagnosis of analog circuits become an important research area where a number of corresponding theories and techniques have been developed
Following the ideas of these researches, this paper proposes two improved fault models with satisfactory fault detection ratio (FDR) based on collaborative analysis of output voltage and supply current
In order to cope with the difficulties of fault diagnosis in analog circuits, a 2D fault model based on collaborative supply current and output voltage is first proposed in this paper
Summary
Over the past two decades, fault detection and diagnosis of analog circuits become an important research area where a number of corresponding theories and techniques have been developed. To achieve detection of parametric faults for analog circuits, Yang et al proposes a complex-circle based fault model [3]. This proposed fault model is improved sequentially by optimal testing frequency selection [12] and fault location [13], the weakness of fault masking still remains. Following the ideas of these researches, this paper proposes two improved fault models with satisfactory FDR based on collaborative analysis of output voltage and supply current. To deal with the ambiguity groups in the fault model, an innovative method of DFT is demonstrated in Section 4 to improve the FIR.
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