Fault indulgent in embedded memory using WCET real-time embedded system

Abstract

The growing density of integration and the increasing percentage of system-on-chip memory occupied by embedded programs have led to an increase in the expected amount of power consumption. In order to reduce the integrity and iterations of the embedded programs the WCET has been implemented. By monitoring the Worst Case Execution time we can reduce the clock cycles required by each instruction of the program, which analogously increases the memory consumption based on both RAM and ROM memory in the embedded system and also power consumption criteria. In this paper, a compiler level optimization, namely WCET-aware rescheduling register allocation, is proposed to achieve WCET minimization for realtime embedded systems. The novelty of the proposed approach is that the effects of register allocation, instruction scheduling, and cluster assignment on the quality of generated code are taken into account for WCET minimization. Three compilation processes are integrated into a single phase balanced result obtained with 6kbytes of ROM reduction from 8kbytes.