Minimizing Schedule Length via Cooperative Register Allocation and Loop Scheduling for Embedded Systems

Abstract

Loops are typically the most computation intensive sections for embedded applications. Therefore, it is important to minimize the overall schedule length for loops during the compilation process. Register allocation and instruction scheduling are two key activities during a compilation process. These two activities exhibit a phase ordering problem: Instruction scheduling before register allocation could lengthen live ranges of variables which will create more conflicts and more costly spills, Register allocation before scheduling may result in the same register assignment to two independent variables which will limit the choices available for scheduling. This paper proposes a cooperative re-scheduling register allocation technique for loops that combines these two critical stages together to minimize the schedule length. The novelty of the proposed approach is that the responsibility for balancing the phase ordering problem lies within the register allocator, which can re-schedule the aggressive initial scheduling to minimize the schedule length. Experimental results show that the proposed approach can reduce overall schedule length by 12% on average compared to previous techniques.