Fault based test minimization for adder and subtractor circuits

Abstract

Major proportion of the manufacturing cost of digital circuits is devoted to testing part. Reduction in the number of tests lowers the manufacturing cost and market price of digital circuits. The main focus of this research work is to minimize the number of tests performed to find faults in combinational circuits. The authors framed a new technique comprising of three phases. The first phase identifies independent faults. The Second phase generates tests for faults identified in first phase. The third phase minimizes the number tests generated in Second phase. Zero One Linear Programming (ZOLP) technique is employed in third phase to minimize the number of tests. The problem is formulated using duality theory of linear programming. Independent fault set identification is modeled as dual and test minimization is modeled as primal. Solution of the dual problem yields a Conditionally Independent Fault Set (CIFS). Solution of the Primal problem minimizes the set of all accumulated test vectors. Two-output adder/ subtractor circuits comprising AND, OR and NOT gates designed for this purpose are used as test bed. The results exhibit considerable reduction in actual test sets. The proposed technique is suitable for any complex digital circuits.