A new approach for test set compaction in combinational circuits

Abstract

In this research paper, the authors propose a new technique for the solution of minimal test generation problem in simple combinational circuits. It consists of two subproblems. First one is the problem of identifying independent faults and generating tests. The second one is the problem of minimizing number of tests using Integer Linear Programming (ILP) technique. It employs the duality theory of linear programming. Independent fault set identification is modeled as dual and test minimization is modeled as primal. Primal solution minimizes the set of all accumulated test vectors. Four Combinational logic circuits comprising AND, OR and NOT gates are experimented with the proposed method. Primal and dual problems are formulated for these circuits. The results show potential for smaller test sets which reduces testing time of complex circuits and thereby reduces manufacturing cost.