Fast reverse converter Architecture for Balanced Five Moduli Set {2n, 2n+1, 2n-1, 2n+1-1, 2n-1-1}

Abstract

In this paper fast residue-to-binary converter for the moduli sets {2n, 2n+1, 2n-1, 2n+1-1, 2n-1-1} will be presented. The reverse converter architecture has three step designs includes Chinese Reminder Theorem (CRT) in first step and mixed radix conversion (MRC) for second and third steps. Comparison with the state-of-the-arts works in literature confirms that the proposed architecture improves the speed of residue-to-binary conversion and has excellence in hardware saving.