Fast quadratic increase of multiport-storage-cell area with port number

Abstract

It is shown that the space required for wordline/bitline routing leads to a quadratic multiport-storage-cell area increase with port number N, dominating from as little as N = 2, N = 6 for small ROM and large SRAM cell types, respectively. Larger N results in enormous area increases (e.g. by a factor of 80 for a 32-port SRAM), making conventional multiport memories unacceptable for most practical applications.