Abstract

We have adapted recently developed techniques for fast-pulsed I-V characterization, to monitor the changes of various trap populations during lifetests of GaN high electron mobility transistors (HEMTs). Unlike other techniques, this approach is rapid and well-suited to repeated characterizations of multiple devices during a lifetest. We monitor qualitatively, the populations of “shallow” traps (those we can change with moderate “pre-treatments”) under the gates, as well as between the gate and drain contacts, and distinguish “slow” and “fast” traps (with time constants greater or less than 10 minutes). Also, we monitor changes in the populations of “deep” traps. Examples are shown from DC and RF lifetests on GaN HEMT devices from one foundry. As-fabricated, these FETs have fast traps under the gate and slow and fast traps in the G-D access region. With lifetest stress (DC or RF), approximately $1\times 10^{12}$ more fast traps per cm $^{2}$ develop in the G-D access region, and about $2\times 10^{12}$ deep traps per cm $^{2}$ develop under the gates, while the other trap populations are not changed.

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