Fast Pipelined Aes Algorithm Implemented on Xilinx Fpgas

Abstract

The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. In the proposed work we present an efficient cryptography hardware implementation and its improvement using pipelines. The algorithm was implemented in FPGA due to its flexibility and reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher throughput and greater parallelism. The VHDL description will be implemented on FPGAs. Modelsim Xilinx Edition will be used for functional simulation and verification of results. Xilinx ISE will be used for synthesis. The Xilinx’s chipscope tool will be used for verifying the results on Spartan 3E FPGA. Fast Pipelined Aes Algorithm Implemented on Xilinx Fpgas