Fast parallel CRC algorithm and implementation on a configurable processor

Abstract

We present a fast cyclic redundancy check (CRC) algorithm that performs CRC computation for any length of message in parallel. For a given message with any length, we first divide the message into blocks, each of which has a fixed size equal to the degree of the generator polynomial. Then we perform CRC computation among the blocks in parallel using Galois field multiplication and accumulation (GFMAC). Theoretically, our fast parallel CRC algorithm can achieve unlimited speedup over the bit-serial algorithm or byte-wise table lookup algorithm at the expense of adding enough GFMAC units. Our algorithm can perform CRC computation for any lengthy message with two to three clock cycles. In practice, we choose to use a configurable processor where a customized instruction is added to perform multiple pairs of GF multiplication and accumulation. For example, a 4-GFMAC implementation can compute a 32-bit CRC in two to three cycles for a 16-byte message. This level of performance is hundreds of times faster than a bit-serial CRC algorithm or tens of times faster than a byte-wise parallel CRC algorithm. The generator polynomial can be chosen to be software programmed or hard-coded. Our algorithm adds only a small number of logical gates to the processor core.