High performance table-based architecture for parallel CRC calculation

Abstract

A high performance table-based architecture implementation for CRC (cyclic redundancy check) algorithms is proposed. The architecture is designed based on a highly parallel CRC algorithm. The algorithm first divides a given message with any length into bytes. Then it performs CRC computation using lookup tables among the divided bytes in parallel. At last, the results are XORed to obtain the CRC value of the given message. The algorithm is table-based and can accelerate different CRC algorithms. Based on the algorithm, the architecture is designed to accelerate CRC algorithms with high parallelism and flexibility. The architecture is configurable and can support CRC algorithms such as CRC32, CRC24, CRC-CCITT, CRC16, CRC8. CRC value of 128-bit input data can be generated in one cycle. Our method also allows calculation over data that is less than 128-bit wide without increasing hardware cost. With 128-bit input each clock cycle, the throughput of the proposed architecture reaches up to 100 Gbps by utilizing 16 KB SRAM (Static Random Access Memory) with about 12% area reduction compared with previous work.