Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator

Abstract

Linear programming optimization is critical to logistics management, engineering designs, and decision making in every area of the economy. Traditional hardware that using GPU and CPU platforms for this purpose is significantly limited by the scaling transistor size. In this paper, an analog in-memory computation circuit is proposed to accelerate linear programming optimization problems. The proposed scheme includes a memristor crossbar array and analogue peripheral circuits that do not need ADC/DAC between each iteration of the algorithm. In addition, we discuss several key parameters related to interconnect parasitics and non-ideal device characteristics to provide practical guidelines. Furthermore, we propose three design schemes to mitigate the computation error that comes from the interconnect resistance in a large-scale crossbar array implementation. Optimal design parameters are quantitatively analyzed under a given number of memristance and array size. It is demonstrated that the proposed accelerator achieves energy consumption, area and delay reductions of ~ 21×, ~151× and ~ 33×, respectively, compared to the 16nm-technology CMOS digital circuits for a 1000×1000 array with a precision of 6-bit