Fast FPGA Placement Using Analytical Optimization

Abstract

FPGA (Field Programmable Gate Arrays) placement consumes half of the runtime of the design flow. As the number of cells are increasing due to increase in design complexity and size, this problem is gaining importance. Typically placement of blocks in FPGA are based on simulated annealing algorithms. Since the FPGA designs are smaller compared with their ASIC counterparts, simulated annealing algorithms are feasible as the runtime to place them is less. However, as the design size and complexity is increasing, simulated annealing algorithms and genetic programming based algorithms tend to be slower. In this paper, our work is targetted towards improving the runtime of placement in FPGAs. We propose a novel algorithm which is based on nonlinear analytical methods. This method uses density penalty approach, wherein, the spreading of blocks across the die is controlled by the square of penalty for the uneven regions across the die. Our method is fast and, when compared with VPR, we improve the runtime by 750% while providing a reasonably good solution for the placement.